drain (Total 32923 Patents Found)

Drain (32923 Patents Found)
An amplifier circuit for detecting low level signals of positive or negative amplitude, and for producing an output pulse whenever the input signals exceed a predetermined threshold level. The threshold level, or sensitivity of the amplifier circuit, is established through use of a pair of operational transconductance ...
A method with and associated apparatus for vibration-filling electrodes in a paste bath. A holding tool connected to a vertical rotary shaft carries the electrode and, arranged above it, a vibration reflection body. The electrode and vibration reflection body are immersed in the paste bath, filling of the electrode is ...
An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first ...
A conduit assembly adapted to be used with a fire sprinkler drain outlet is disclosed. The conduit assembly includes a conduit segment including (i) an intake end portion having a proximal opening configured to receive the fire sprinkler drain outlet therein, and (ii) a discharge end portion defining a terminal end of ...
A PMOS thin film transistor including an LDD region may be fabricated by implanting an ion dose at a specific concentration in order to form the LDD region with a certain range of sheet resistance at both ends of a gate electrode of the PMOS thin film transistor. A buffer layer, an active layer, the gate insulating lay...
A transistor ( 10 ) is formed on a semiconductor substrate ( 12 ) with a first surface ( 19 ) for forming a channel ( 40 ). A gate dielectric ( 22 ) has a first thickness overlying a first portion of the channel, and a dielectric film ( 20 ) overlies a second portion of the channel and has a second thickness greater th...
A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the sh...
A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer...
The disclosure relates to a semiconductor device having an isolation structure with a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; and a strained material in the cavity and extending above the top surface. The strained material has an upper portion having a ...
An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has a...
A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the ...
An improved trench drain filter and modular system therefor for intercepting and treating run off water in a trench drain before discharge into a drainage system. The filter elements include a perforated pipe covered with one or more layers of geotextile material, which is, in turn, covered with a permeable fabric memb...
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. ...
A pipe coupling with a water seal between the sinks of a draining board and the drain pipe (9), comprising a collecting pipe (4) having connected thereto one or a plurality of jointing pipes (3) for sink connecting tubes (2) and a water seal forming pipe element (7) as well as a jointing pipe (6) for said drain pipe (9...
A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation ...
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl 2 as an etchant during the epitaxial formation of the S/D regions. The mechanisms involve using an asymmetric cyclic deposition and etch (ACDE) process that forms a preparation layer enable epitaxi...
A drain structure for a fluid filter includes a cap internally forming a drain hole. The cap receives a valve member urged by an urging means in a direction, in which the valve member blocks the drain hole. Normally, the drain hole is blocked with a drain member. When fluid is drained from the drain hole, the drain mem...
Exemplary embodiments provide methods and systems for fabricating a metal source-drain stressor in a MOS device channel having improved tensile stress. Aspects of exemplary embodiment include forming a recess in source and drain areas; forming a metal contact layer on surfaces of the recess that achieves low contact re...
A method of manufacturing a semiconductor device that eliminates the N + implant by replacement with resist spacers on n-channel gate structures and a standard Mdd implant. The N + implant is thereby eliminated from the n-channel transistors and is replaced by an Mdd implant. The Mdd implant is simultaneously implant...
A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysil...
High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxi...
A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a ph...
A liquid crystal display device having a plurality of data lines and a plurality of gate lines arranged perpendicular to each other and a plurality of thin film transistors and pixel electrodes formed for respective pixels includes a substrate and a gate electrode on the substrate. A first insulating layer is formed on...